When a semiconductor chip is tested for the first time, it is tested in wafer form; that is, there are many chips on a single wafer at the time of first test. Testing is accomplished by alignment of a probe card having as many probe needles as does the chip have connection pads. The probe needles are electrically connected to the testing machine allowing that machine to interconnect with the chip under test.
Alignment is accomplished either by manually (visually) scanning the wafer with the aid of a microscope or by viewing the wafer on a video monitor, while manually moving the wafer stage in the X and Y (lateral) directions and while, at the same time, adjusting the stage for axial rotation of the wafer to correct for rotational alignment error. The process is tedious and prone to error since it relies completely upon human judgment.
In recent years, it has become a common practice to include fusible links as a part of certaim chip designs to allow selection or deselection of circuits on the chip at the time of initial testing. This practice has reulted in even closer attention being given to the alignment problem stated, above, so that a laser beam may be closely aligned to a given fusible link thereby allowing the selected link to be blown by the application of laser energy to it.
The laser "repair" system has the capability of recognizing certain highly reflective geometries (a key pattern) on a wafer with an accuracy within approximately 150 microns of its actual location. Alignment of the laser coordinate system or the wafer stage is then made to that alignment key pattern. Prior art practice is to place the key patterns in the scribe grid which lies between chips on the wafer. While this practice avoids the use of valuable chip "real estate", frequently the keys so placed are not sufficient to allow both X, Y offset correction, theta rotational correction, X-scale magnification correction and Y-scale magnification correction.
Very large scale integrated (VLSI) circuits are made by direct wafer steppers (DSW). This means that every print of a reticle on the wafer can have a translational and/or rotational misalignment with respect to a virtual absolute grid. Such a reticle usually contains at least two (or more) chips in a cluster for several reasons. First, if the reticle contains more than one chip, less stepping operations are required to step the chips across the wafer. Second, if more than one identical chip is on one reticle, a mask comparator can be used to find a random mask defect by comparing a video image of one chip to the next chip in the same reticle. Any differences may be legitimately attributed to random defects. With such a cluster arrangement, a chip may have different scribe grids on different sides of the chip. For example, where there are two chips in a reticle, there will be a full scribe line between the two chips in the middle of the reticle and one-half scribe line on the right, left, top and bottom sides of the reticle. Toward the edge of the reticle, and in place of the half scribe line, one chip could have a full scribe line and the other, none at all.
Where chips are stepped repetitively across a wafer, the full scribeline to the right of one chip is, at the same time, the left full scribeline of the chip stepped next to it. The scribeline between the chips is precisely that; a scribeline, and it has a width just sufficient for scribing a wafer for separation of the chips. In contrast, the scribeline toward the edge of the reticle must contain the alignment keys for the stepper alignment. The two chips on the reticle are self aligned with respect to each other, but this two chip cluster must be accurately aligned to the corresponding image on the wafer. Thus the scribeline around the perimeter of the reticle can have a different width than the scribeline in the middle of the reticle.
One can now appreciate the difference between the reticle alignment keys and the laser alignment keys. The reticle alignment keys are required only once per reticle but the laser alignment keys are required for every chip. It is absolutely impossible to put the laser alignment keys into the scribe grid if the scribe grid in the middle of the reticle has a width different from that in the perimeter of the reticle.
There are two expensive ways to solve the problem in the prior art. First, the scribe grid in the middle of the reticle can be made as wide as the larger grid at the perimeter of the reticle (which is larger because it contains the reticle alignment keys). This wastes silicon area and does not solve the laser key correlation problem, yet to be described. Second, the scribe at the edge (or perimeter) of the reticle could be made to equal a full width scribeline, all the way around, so that when the reticle is stepped, one full width scribeline is touching another. This method would correlate the laser alignment keys to the chip but there would be adjacent keys in each corner, one belonging to the left chip and one to the right chip and the automatic alignment system might very well mistake one for the other. Another problem with the latter approach is that (as above) it wastes too much silicon area.
Since many advanced steppers do a site by site alignment, the blind stepping accuracy is quite poor; for example, three micron accuracy for blind stepping from one reticle image to the next. For any laser alignment key placement method in which the alignment in the right hand scribe of the reticle serves as the left hand alignment key for the chip to the right side, the laser or prober alignment accuracy is the built in inaccuracy plus the blind stepping inaccuracy of the DSW. This total inaccuracy affects not only the X and Y offset, but also the magnification sensitivity and in most cases leads to a miss of the fusible link to be repaired.